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SPI I2C Cheatsheet
Reference SPI modes, convert I2C addresses, and estimate practical pull-up values.
SPI mode quick reference
Check idle clock level and which edge samples incoming data.
| Mode | CPOL/CPHA | Idle | Sample | Shift |
|---|---|---|---|---|
| Mode 0 | (0,0) | Low | Rising | Falling |
| Mode 1 | (0,1) | Low | Falling | Rising |
| Mode 2 | (1,0) | High | Falling | Rising |
| Mode 3 | (1,1) | High | Rising | Falling |
Wiring mnemonic
Controller-out is MOSI/COPI, controller-in is MISO/CIPO, clock is SCLK, and each target needs its own chip-select.
Bring-up order
Confirm voltage levels, then CS polarity, then mode, then bit order, then maximum clock rate.
I2C address helper
Enter a 7-bit slave address to get the transmitted read and write bytes.
Write byte
0x78
01111000
Read byte
0x79
01111001
7-bit address: 0x3C
On the bus, the address is shifted left by one and the lowest bit becomes the R/W flag.
I2C pull-up guidance
Use the table for quick defaults, then sanity-check with estimated bus capacitance and sink current.
100 kHz
4.7k - 10k typical
Spec rise time target: 1000 ns
400 kHz
2.2k - 4.7k typical
Spec rise time target: 300 ns
1 MHz
1k - 2.2k depending on bus capacitance
Spec rise time target: 120 ns
Minimum resistor
1.10 kOhm
Keeps sink current near or below 3 mA.
Maximum resistor
3.54 kOhm
Based on 400 kHz rise-time limit and RC charging.
Suggested values
1.2k, 1.5k, 1.8k, 2.2k, 2.7k, 3.3k
4.7k would sink about 0.70 mA at this supply.
Bus debug checklist
I2C no-ack
Check 7-bit vs 8-bit address confusion first, then pull-ups, then whether the target is held in reset or busy with clock stretching.
SPI all-zero or all-ones data
Look for wrong mode, wrong chip-select timing, missing common ground, or a target that requires a dummy byte before returning data.
Scope sanity checks
I2C should idle high on both lines. SPI clock should idle at the level implied by CPOL and only toggle while CS is asserted.